CS221 Lecture: Introduction to Digital Logic last revised 10/17/95
Objectives:
1. Ability to read simple logic diagrams
2. Ability to design simple combinatorial circuits
Materials: Samples of logic technologies
I. Introduction
A. From physics we learn that all the complexity of the universe is built
up from combinations of certain fundamental building blocks: electrons,
protons, neutrons (or quarks if you will.) In like manner, all the
complexity of digital computers is built up from fundamental building
blocks called GATES.
1. A gate is an electronic circuit having one or more inputs and one
output, each of which can be in one of two states, commonly called 0
and 1. Further, the output at any time is some function of the inputs.
2. Gates can be realized in many different ways, but we will say little
about this. We should note that the generations of computer hardware
are largely distinguished by the technology used to realize gates:
relays (0); vacuum tubes (1); transistors (2); integrated circuits
(3). With all pre-IC technologies, a gate would consist of a number
of discrete components wired together on a circuit board (cf sample
transistor board); with IC technologies, one or more gates are
completely contained on a silicon chip.
B. For our purposes, we will think of a gate as a "black box" having one or
more inputs plus a single output.
1. The voltage at the output of the gate is some function of the
input voltages.
2. Example: a two-input gate
________
V1in -----| |
| |---- Vout = f(V1in, V2in)
V2in -----|_______|
3. Gates are designed so that they respond to two discrete voltages -
one of which is associated with the value 0 (false) and the other
with the value 1 (true). With the kinds of gates we will be using
(TTL and CMOS), the value 0 (as input or output) will normally be
represented by a voltage level close to 0. The value 1 will normally
be represented by a voltage level of about 5 volts. (Some other
gate technologies use other values.)
4. In actual practice, any gate technology will accept a RANGE of
voltages for each logic value. For example, with TTL gates (the kind
we will be using), the following rules hold:
a. Any voltage between 0 and 0.8 Volts is regarded as low, and is
interpreted as a zero.
b. Any voltage between 2 and 5 volts is regarded as high, and is
interpreted as a one.
c. Any voltage between 0.8 and 2 volts constitutes an undefined input.
The output of any gate which has any undefined input can be 0, 1,
or undefined itself.
d. Any voltage less than 0 or greater than 5 volts is illegal, and
may physically destroy the gate.
5. Actually, the convention we have been describing is one of two
possible options, known as positive logic. It is also possible to
adopt the convention of letting a low voltage (between 0 and 0.8 volts)
represent a 1, and a high voltage (between 2 and 5 volts) represent a
0. This yields negative logic - but we won't discuss this further now.
6. To keep our discussion simple, we normally describe the inputs and
outputs of a gate as being L or H or 0 or 1, rather than worrying
about the specific voltages.
C. We will represent the behavior of a gate by a table of combinations or
truth table which shows the output of the gate for each possible
combination of inputs. For example, a 2 input AND gate has truth table:
Inputs Output _____
x y z x ----| |
| |---- z
0 0 0 y ----|___|
0 1 0
1 0 0 Note: we are using a nondescript
1 1 1 shape for our black box. Later we
will see there is a specal shape
for certain types of gates.
1. Note that for a gate with 1 input there are 4 possible truth tables,
representing:
- a gate whose output is always 0, regardless of input
- a gate whose output is always 1, regardless of input
- a gate whose output is the same as its input
- a gate whose output is the opposite of its input:
x z
0 1
1 0
a. Of these, only the last two are of any interest at all, and
the last one is most useful.
b. The gate whose output is the same as its input is often used in
situations where it is necessary to amplify a signal to drive
a number of gates. Such a device is called a BUFFER:
symbol: ___|\___
|/
c. The gate whose output is the opposite of its input is called an
INVERTER. Two symbols can be used for this function:
____|\o____ or ____o|\____
|/ |/
- Note use of the "bubble" to symbolize inversion of the logic
sense. In the first case, the symbolism is that the output of
the gate is the opposite of that from a simple buffer. In the
second case, the symbolism is that the output of the gate is
the same as that of a simple buffer whose input has been
inverted. Obviously, the two symbols describe two ways of
looking at the SAME BEHAVIOR, and so can be used interchangeably
to describe the same physical circuit.
2. For a gate with 2 inputs, there would be 16 possible truth tables.
For each of the 4 combinations of the 2 inputs, we could choose one
of two outputs. Thus, there are 2^4 possible truth tables. Again,
only a limited number are of interest - we defer discussion until
later.
3. In general, for a gate with n inputs, there are 2^(2^n) possible truth
tables.
II. Boolean Algebra
A. To describe the behavior of networks of gates, we use a notational system
called boolean algebra (or switching algebra). In this system, we have
only two values, 0 and 1, and three primative operations:
_
1. Inversion or complementation, written x or x'. (Note - in these notes
I will use the symbol x' because it's easier to type!):
x x'
0 1
1 0
2. Addition or Logical or, written x + y:
x y x + y
0 0 0
0 1 1
1 0 1
1 1 1 Note: 1 + 1 = 1!
3. Multiplication or Logical and, written x * y or xy:
x y xy
0 0 0
0 1 0
1 0 0
1 1 1
B. As in any algebraic system, more complex operations can be built up out
of the primative operations, with operator precedence rules or
parentheses for grouping - e.g:
x' + xy = (x') + (xy) - truth table:
x y x' xy x'+xy
0 0 1 0 1
0 1 1 0 1
1 0 0 0 0
1 1 0 1 1
C. As in other algebras, there are certain properties that govern the
behavior of more complicated expressions, such as associativity,
commutativity, and distributivity. However, whereas these are axioms
for most algebraic systems, for boolean algebra they are theorems since
any one of them can be proved from the definitions above by exhaustion
(perfect induction). Here are some of the key properties:
For all x, y, z:
Commutativity: x + y = y + x
x * y = y * x
Associativity: x + (y + z) = (x + y) + z
x * (y * z) = (x * y) * z
Distributivity: x * (y + z) = (x * y) + (x * z)
x + (y * z) = (x + y) * (x + z) !!
Properties of 0: x + 0 = 0 + x = x (0 is identify for +)
x * 0 = 0 * x = 0 (0 is null for *)
x * x' = 0
Properties of 1: x + 1 = 1 + x = 1 (1 is null for +)
x * 1 = 1 * x = x (1 is identify for *)
x + x' = 1
Idempotence: x + x = x
x * x = x
not --> Involution: (x')' = x
in Stallings
Demorgan's Theorems: (x + y)' = x' * y'
(x * y)' = x' + y'
D. As an illustration of proof by perfect induction, we prove the first
form of Demorgan's theorem:
x y x+y (x+y)' x' y' x'*y'
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
III. Realization of boolean functions
A. Crucial to the design of computer systems is the ability to realize
circuits composed of gates whose output corresponds to some boolean
function of its inputs. To do this, we usually use certain types of
gates as building blocks, with more complex functions realized by
combinations of gates in which the output of one gate becomes an input
to another.
B. While we could theoretically implement any truth table as a hardware
primative, most designs are built around a limited number of basic
functions implemented in hardware. We have met one already, the
inverter. Two-input functions of interest include:
____
1. 2-input AND: symbol: x ---| \ z = xy
| )--- z
y ---|____/
_____
2. 2-input OR: symbol: x ---\ \ z = x + y
) >--- z
y ---/____/
____
3. 2-input NAND: symbol: x ---| \ z = (xy)'
| )o-- z
y ---|____/
Note: in boolean expressions NAND is sometimes written with
the Sheffer stroke - i.e.
^
x | y = (xy)'
_____
4. 2-input NOR: symbol: x ---\ \ z = (x+y)'
) >o-- z
y ---/____/
Note: in boolean expressions NOR is sometimes written with
the Pierce arrow - i.e.
x | y = (x + y)'
v
5. The latter two are of particular interest, for two reasons:
a. Most of the transistor circuits used in realizing gates have the
effect of inverting the signal passing through them. Thus, NAND
and NOR can generally be realized more simply than AND or OR.
b. NAND and NOR are logically complete. Given either one, it is
possible to realize any boolean function. Examples:
____
- Invert realized using NAND: x -+--| \ z = (xx)' = x'
| | )o--- z
+--|____/
____
- AND realized using NAND: x ----| \ |\
| )o--o| >--- z
y ----|____/ |/
z = ((xy)')' = xy
|\ ____
- OR realized using NAND: x --| >o--| \
|/ | \
| )o--- z
|\ | /
y --| >o--|____/
|/
z = (x'y')' = x + y
6. For any particular gate technology, usually one of the latter two will
be more easily realized. In the case of TTL technology, this is NAND.
For consistency, we will work most of our examples for the rest of
this unit using NAND.
7. Note that DeMorgan's theorem suggests an alternate symbol for NAND:
_____
(xy)' = x' + y' ==> x ---o\ \
) >--- z
y ---o/____/
z = x' + y'
- This symbol says that the output of a NAND gate is the same as that
of an or gate presented with the inverse of the inputs presented to
the NAND. (The first symbol said that the output of a NAND gate is
the inverse of that of an AND gate presented with the same inputs.)
- Note that both symbols describe exactly the same gate - a NAND
gate may be drawn either way. By convention, the symbol that is
chosen is the one that most clearly represents the intended use
of the gate - e.g. the above diagram for an OR implemented with
NANDS is more conventionally drawn as follows:
|\ _____
- OR realized using NAND: x --| >o--o\ \
|/ \ \
) >--- z
|\ / /
y --| >o--o/____/
|/
z = (x')' + (y')' = x + y
C. Two other functions of two inputs are of some considerable interest
1. XOR: symbol: Truth table:
____ x y x O+ y
x ---\-\ \
) ) >--- z 0 0 0
y ---/-/___/ 0 1 1
1 0 1
z = x O+ y 1 1 0
Note that x XOR y is true iff x <> y
2. XNOR (Coincidence):
____ x y x O. y
x ---\-\ \
) ) >o-- z 0 0 1
y ---/-/___/ 0 1 0
1 0 0
z = x O. y 1 1 1
Note that x XNOR y is true iff x = y. (XNOR and XOR are complements)
3. Both can be realized using other types of gates. For example, the
following is a realization of XOR using NAND - assuming that both the
inputs and their complements are available. (If not, two inverters
would also be needed):
____
x ---| \ _______ z = ((xy')')' + ((x'y)')'
| )o----o\ \ = xy' + x'y
y'---|____/ \ \ = x O+ y
____ ) >--- z
x'---| \ / /
| )o----o/______/
y ---|____/
D. We often find gates with more than two inputs, but they are usually
extensions of the types of 2-input gates we have been using. For
example, 4-input NAND:
symbol: a b c d z
____ 0 0 0 0 1
a ---| \ 0 0 0 1 1
b ---| )__ z 0 0 1 0 1
c ---| ) 0 0 1 1 1
d ---|____/ 0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
IV. Realizing boolean functions using NAND gates. (Similar techniques could
be developed for other types)
A. Observe that any boolean function can be written in sum-of-products
form by using its truth table. Example:
z = a O+ (bc)
a b c z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
1. Find each row in the truth table where the output is 1. This will
contribute one term to the sum. Thus, this function can be
represented as a sum of four products.
2. Each product will contain each of the inputs either plain or
complemented. An input will appear plain if the row in question
contains a value of 1 for that input, and complemented if it contains
a 0. Thus, the fourth row in the truth table (the first containing a
1 output) gives rise to the term a'bc.
3. A function equivalent to our original function is therefore
z = a'bc + ab'c' + ab'c + abc'
- Note that each term is 1 for exactly one combination of inputs and 0
for all others.
- Each term therefore gives us one of the 1's of the function.
B. A boolean function in sum of products form can be realized by NAND gates
directly:
1. Realize each term by using a NAND gate with as many inputs as there
are inputs to the overall function. Each gate input goes either to one
of the function inputs or its complement as specified in the term.
(We assume we have convenient access to each input as well as its
complement. If not, we realize the complements using inverters - but
this is usually not necessary.)
2. Sum all of the terms using a NAND gate (represented in its alternate
form) with as many inputs as there are terms.
The above:
____
a'---| \
b ---| )o--------+
c ---|____/ |
____ |
a ---| \ |
b'---| )o-----+ | _______
c'---|____/ | +--o\ \
+-----o \ \___ z
____ +-----o / /
a ---| \ | +--o/______/
b'---| )o-----+ |
c ---|____/ |
____ |
a ---| \ |
b ---| )o--------+
c'---|____/
z = a'bc + ab'c' + ab'c + abc'
3. This realization is called a two-level realization, since the input
must pass through two gate levels before arriving at the output. This
is of some significance, since all gates have a certain finite
propagation delay. Note that, apart from a special-purpose gate,
two logic levels is the best one can do for most functions.
C. While the method outlined above gives a realization that cannot be
improved on in terms of number of levels, it is not optimal in terms of
number of gates.
1. Observe that our sum of products form can be simplified
by the properties of boolean algebra as follows:
a'bc + ab'c' + ab'c + abc' = a'bc + a(b'c' + b'c + bc')
= a'bc + a(b'c' + b'c' + b'c + bc')
= a'bc + a(b'c' + b'c + b'c' + bc')
= a'bc + a(b'(c'+c) + c'(b'+b))
= a'bc + a(b'(1) + c'(1))
= a'bc + a(b'+c')
= a'bc + ab' + ac'
2. This yields the simplified realization:
____
a'---| \
b ---| )o--------+
c ---|____/ |
____ | _______
a ---| \ +--o\ \
| )o-----------o ) >--- z
b'---|____/ +--o/______/
|
____ |
a ---| \ |
| )o--------+
c'---|____/
3. This simplification would result in a considerable cost savings in
construction.
a. The original circuit needed:
4 3-input NAND gates
1 4-input NAND gate
Since 3-input gates come 3 to a chip and 4-input gates come 2 to a
chip, this amounts to two full chips (one of each kind, with one
4-input gate used as a 3-input gate.)
b. The new circuit requires:
2 3-input gates
2 2-input gates
Since 4-input gates come 4 to a chip, this circuit would still
need two chips, but there would now be 1 3-input gate and 2 2-input
gates left over for other parts of the system to use.
D. For functions of four variables or less, this simplification can be done
more simply by the use of a Karnaugh map.
1. Example, for the above:
ab/c 0 1
00 0 0
01 0 1
11 1 0 (Note order of values!)
10 1 1
(Show covering)
2. Example for four variables:
z = a'bc'd' + a'b'c' + a'c'd + ab'cd + ab'c' + ab'd'
ab/cd 00 01 11 10
00 1 1 0 0
01 1 1 0 0
11 0 0 0 0
10 1 1 1 1
(Show covering)
Simplified form: a'c' + ab'
3. In using this method, we cover all of the 1's by using maximal
subcubes of one of the following forms:
show 8's both ways; 4's square and horizontal and vertical;
4's square with side wrap, top wrap; 4's square at corners;
2's horizontal, vertical, wrap at sides, top;
1.
4. The method works because the values are ordered in such a way that
any two horizontally or vertically adjacent entries differ in exactly
one input, whose value is irrelevant if both squares contain a 1.
5. In setting up functions to be minimized using a Karnaugh map, it is
often helpful to use a different notation for the function. Basically,
we represent each 1 of the function by a decimal number that is the
equivalent of the binary number representing the values of the inputs.
a. Example: z = a'b'cd + ab'c'd can be written
__
z = \ (3, 9)
/__
because a'b'cd corresponds to an input pattern of 0011 = decimal 3
and ab'c'd corresponds to an input pattern of 1001 = decimal 9
b. In doing this, one must be sure to include all the variables in
each term.
Example: z = a'cd + abc
must be written as
z = a'b'cd + a'bcd + abcd' + abcd
__
= \ (3, 7, 14, 15)
/__
E. Often, in designing a logic circuit, it happens that certain input
patterns are known to not be possible. Thus, the output produced for
these patterns is irrelevant. We refer to this as a don't care condition.
1. Example: a 7-segment decoder translates the binary representation
of a decimal digit into 7 outputs corresponding to the 7 segments
of an LED display. Consider just the output for the top bar:
=====
/ /
-----
/ /
-----
This needs to be on when the input is 0, 2, 3, 5, 6, 7, 8, or 9, and
off when the input is 1 or 4. We don't care what its state is for
inputs 10-15, since these don't correspond to any decimal digit and
thus presumably cannot occur. Thus, our function for the top bar is
__
a = \ (0, 2, 3, 5, 6, 7, 8, 9) + d(10, 11, 12, 13, 14, 15)
/__
2. In constructing the map, we put 1's for the 1's of the function,
d's for the don't cares, and 0's for everything else.
Example:
00 01 11 10
00 1 0 1 1
01 0 1 1 1
11 d d d d
10 1 1 d d
3. In constructing a covering, we must cover ALL the one's, but only
cover d's which help us to construct bigger sub-cubes. For example,
in the above it would be convenient to cover all the d's.
(Show covering)
4. However, if we consider the following map for the bottom segment of
the seven segment display, we find that we only choose to cover 4 of
the 6 d's
00 01 11 10
00 1 0 1 1
01 0 1 0 1
11 d d d d
10 1 0 d d
(Show covering)
F. When working with NOR logic, it is convenient to use a mirror-image
technique:
1. Working directly with the truth table, we can represent function as a
product of sums, derived by looking at the zeroes of truth table.
Each input appears in ordinary form if the row contains
a zero; complemented form if it contains a 1. Example: our original
example z = a O+ (bc) becomes
z = (a + b + c)(a + b + c')(a + b' + c)(a' + b' + c')
2. We can realize with a product of sums with one NOR gate for each
factor plus one NOR (drawn in dual form) to multiply all factors.
Example:
______
a --\ \
b -- ) >o-----------+
c --/_____/ |
______ |
a --\ \ |
b -- ) >o-------+ | _______
c'--/_____/ | +---o| \
+-------o| ) ____ z
______ +-------o| )
a --\ \ | +---o|_______/
b'-- ) >o-------+ |
c --/_____/ |
______ |
a'--\ \ |
b'-- ) >o-----------+
c'--/_____/
3. Using Karnaugh-map minimization, we seek to cover ZEROES, and put
the variable in the expression in straight form if it is a zero and
complemented if it is a one.
Example: map for the above:
ab/c 0 1
00 0 0
01 0 1
11 1 0
10 1 1
(Show covering)
Simplified expression is (a + c)(a + b)(a' + b' + c')
G. Another minimization technique, discussed in some texts, is the use of
Quine-McCluskey tables. We will not discuss the method here, except
to note the following comparison vis-a-vis Karnaugh maps.
1. Advantages of Quine-McCluskey
a. Not limited to functions of 4 variables (as Karnaugh maps are
for all practical purposes.)
b. Easy to automate
2. Disadvantage of Quine-McCluskey: slower and less visual for use
manually.
Copyright ©1998 - Russell C. Bjork