CS311 Lecture: Sequential Circuits Last revised 8/10/2001
Materials:
1. LogicSim 3.0 and data files - Note that LogicSim should be started from
the PROJECTION folder to ensure loading custom components
I. Introduction
- ------------
A. Thus far, we have been discussing COMBINATORIAL logic circuits.
These have the property that the output at any time is a boolean function
of the inputs (with some propagation delay when inputs change).
B. Complete computer systems also require circuits that have MEMORY -
that is, circuits whose output can be a function of the input AT SOME
TIME in the past. Such circuits are used for:
1. Internal memory: registers, main memory
2. Control circuits that cycle the system through the series of steps
comprising the algorithm for a given task. (The system must keep
track of its state - what step it is currently on - in order to
know what to do next.
II. Building Memory elements with gates.
-- -------- ------ -------- ---- -----
A. It turns out to be quite easy to use our combinatorial building blocks
to construct a circuit that has memory - i.e. whose output is a function
of past as well as present inputs.
B. The following is an example of such a circuit, called a flip-flop:
S _____
--------| \
| )o---+------ Q
+--|_____/ |
|______________)_
______________| |
| _____ |
+--| \ |
| )o-----+---- Q'
--------|_____/
R
Observe:
1. When both S and R are high, there are two stable states:
a. If Q is low, then Q' is high (since the lower gate now has one low
input and one high.) This state is stable, since the upper
NAND gate now has two high inputs, making its output low.
b. If Q is high, then Q' is low (since the lower gate has both inputs
high). This state is also stable, since the upper NAND gate has one
low input and one high input, making its output high.
c. When the circuit is first turned on, the flip flop will go into one
of these two states non-deterministically. (Actually, slight
physical differences in the transistors in the two gates will
usually serve to decide the state.)
2. Relationship of Q and Q' when in a stable state: they are inverses
(hence the choice of labels Q and Q')
3. Effect of momentarily setting either S or R to 0
a. If the flip-flop is in the stable state with Q low then setting R
low has no effect. However, setting S low flips the state to
the state with Q high, where the circuit will remain even after
S returns to high.
b. If the flip-flop is in the stable state with Q high then setting S
low has no effect. However, setting R low flips the state to
the state with Q low, where the circuit will remain even after
R returns to high.
4. Effect of momentarily setting both S and R low:
a. If both S and R are low, then both Q and Q' go high, since each
gate now has one low input. This, of course, violates the
intention of the labels that Q and Q' should be opposites.
b. If both S and R are not restored to the high state at the same time,
the state of the flip flop is intedeterminate: it will settle into
one of the two stable states. Which one, however, cannot be
predicted.
c. For these reasons, having both R and S low at the same time is
regarded as an illegal input pattern for this kind of flip-flop.
5. DEMONSTRATE (File Asynchronous SR flip-flop)
NOTE: Start up LogicSym from PROJECTION folder to get additional
components before double-clicking a file
6. This is variously called an RS flip-flop or an SR flip-flop, and has
its own special symbol:
_____
S--o| |--- Q (Note the use of bubbles to signify
| | that the S and R inputs are
| |\ activated by a LOW input.)
R--o| |--- Q'
-----
7. One can build a similar circuit from NOR gates - but we won't pursue
this here.
C. One important characteristic of the flip flop we have been considering is
that it is ASYNCHRONOUS - that is, the output changes almost
instantaneously when the input changes. (There is a slight delay due to
internal switching times of the gate.) One can also build a clocked
flip flop, in which the state changes only when a special clock pulse is
received. This makes it possible to synchronize state changes. (Such
a device is said to operate SYNCHRONOUSLY)
1. The following has the property that state changes occur only when
the clock input is high:
S _____ _____
--------| \ | \ Q
| A )o----| C )o--+-----
+--|_____/ +--|_____/ |
| | |
-----+ +-------------)--+
Clock | ______________| |
| _____ | _____ |
+--| \ +--| \ |
| B )o----| D )o-----+--
--------|_____/ |_____/ Q'
R
a. Observe that the gates labelled C and D are, in fact, an RS
flip flop (with active low set/reset) of the sort we described
earlier. The inputs to this flip flop are the outputs of the
gates labelled A and B.
b. When the clock input is low, the outputs of both gates A and B
are necessarily high - which leaves the state of gates C and D
unchanged, regardless of the external inputs.
c. When the clock input is high, a high on either S or R becomes a
low at the output of gate A or B (as the case may be), which in
turn sets or clears the flip-flop composed of gates C and D.
d. This kind of flip-flop is called a level-triggered flip-flop or
a LATCH.
e. This circuit has the following symbol:
_____
S---| |--- Q (Note no bubbles on the inputs;
| | the S and R inputs are
| |\ activated by a HIGH input.)
R---| |--- Q'
-----
|
Enable
f. DEMONSTRATE (file Level-triggered SR flip flop)
2. More commonly, clocked flip-flops are constructed to change state
on a PULSE or an EDGE. For example, the following flip-flop changes
state only when the clock input goes from high to low. (It is
required that the S and R inputs do not change during the period that
the clock input is high):
S _____ _____ _____ _____
--------| \ | \ | \ | \ Q
| A )o----| C )o-+------| E )o----| G )o--+-------
+--|_____/ +--|_____/ | +--|_____/ +--|_____/ |
| | | | | |
| +------------)-+ | +-------------)--+
| |\ | | | | |
-----+--| >o------------------)-)-+ | |
Clock | |/ | | | | |
| _____________| | | ______________| |
| _____ | _____ | | _____ | _____ |
+--| \ +--| \ | +--| \ +--| \ |
| B )o----| D )o---+----| F )o----| H )o-----+----
--------|_____/ |_____/ |_____/ |_____/ Q'
R
a. Gates A..D form a level-triggered RS flip flop, as above.
b. Gates E..H likeswise form a level-triggered RS flip flop. The
outputs of the first flip-flop become the inputs of the second.
(This configuration is called a MASTER-SLAVE configuration.
The first flip-flop (A..D) is the master; the second (E..H) is
the slave.)
c. Both flip-flops share a common clock; but the clock is inverted
between them so that the master flip-flop accepts input only when
the clock is high and the slave only when the clock is low.
d. Consider, now, what happens when the flip-flop clock input is
presented with a clock pulse having the following waveform:
_
____________| |________________
i. During the period that the clock is low, the master flip flop
holds whatever state it is in, regardless of input.
ii. During this same period, the slave flip flop is either being
set or cleared by the output of the master flip flop; but in
either case since the master does not change the slave does
not change either.
iii. When the clock goes high, the master's state may change as
a result of the external inputs. However, since the clock to
the slave is inverted, whatever the master does cannot now
affect the slave. (Note: we assume that the external inputs
do NOT change during the brief period that the clock is high.
This is a requirement that designers using this kind of
flip-flop must comply with.)
iv. Finally, when the clock goes low again, whatever new state the
master is in is transferred to the slave, after which neither
flip-flop changes state until the next clock pulse.
v. Thus, to an outside observer seeing only the R, S, and clock
inputs and the Q and Q' outputs, it appears that the flip
flop's state changes are triggered by the falling edge of the
clock pulse. (The internal change of the master is not seen
externally.) Hence, we call such a flip flop a PULSE TRIGGERED
FLIP-FLOP.
vi. A somewhat different circuit can yield an EDGE TRIGGERED
FLIP-FLOP that does not require the input to be stable during
the entire high part of the clock pulse (as this circuit does)
but only that it be stable for a certain interval (the
setup time) before the falling edge. (This allows the use
of square waves as clock pulses.) One can also build edge
triggered flip-flops that change state on the rising edge of
a clock pulse.
vii. It should also be noted that the exact circuit given here is
not necessarily used in actual commercial IC's. (It is actually
more suitable when building up a flip flop from SSI gates.)
e. This flip-flop can be described by the following table, which shows
the state the flip-flop will be in after a clock pulse given its
state before the pulse and inputs at the time of the pulse:
Q S R Q
before after
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 -- error
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 -- error
f. DEMONSTRATE (File Clocked SR flip flop)
g. The following symbols can be used for pulse or edge-triggered RS
flip-flops:
_______ _______
| | | |
--|S Q |--- ---|S Q |---
| | | |
--|> | --o|> |
| |\ | |\
--|R Q'|--- ---|R Q'|---
|_____| |_____|
Transition is triggered by Transition is triggered by
rising edge of clock falling edge of clock
E. Beyond the RS flip flop, two other types of flip-flop are of interest:
1. D flip-flop (can be either level-triggered (latch) or clocked):
a. Symbol
-------
---|D Q |---
| |
--o|> |
| |\
| Q'|---
-------
b. Behavior:
Q D Q
before after
0 0 0
0 1 1
1 0 0
1 1 1
observe: state after is only a function of D - i.e. the flip-flop
"remembers" the D value at the last clock.
c. A D flip flop could be realized from an RS by adding an inverter:
-------
D---+-------|S Q |----- Q
| | |
CL--)------o|> |
| |\ | |\
--| >o--|R Q'|----- Q'
|/ -------
Note that whether the D is level-triggered or edge-triggered
depends on the RS used to build it.
i. DEMONSTRATE D-Latch
ii. DEMONSTRATE Clocked D flip flop
2. JK flip-flop: (always clocked):
a. Symbol
-------
---|J Q |---
| |
--o|> |
| |\
---|K Q'|---
-------
o
|
b. Behavior:
Q J K Q
before after
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
observe: J,K = 0 ==> Q unchanged
J = 1, K = 0 ==> Q <- 1 (set)
J = 0, K = 1 ==> Q <- 0 (reset)
J,K = 1 ==> Q complemented
c. A JK flip flop could be realized from an RS as follows:
Preset
|
+------------------)---------+
| _____ o |
+----| \ ------- |
| )---|S Q |---+--)-------- Q
J --------------|_____/ | | | |
| | | |
CL-------------------------o|> | | |
_____ | | | |
K --------------| \ | |\ | |
| )---|R Q'|---)--+-------- Q'
+----|_____/ ------- |
| o |
+------------------)------+
|
Clear
(Note: in practice, the two and gates on the inputs are folded
with the NAND gates of the SR, using two 3-input NANDS in place
of two 2-input ANDS and 2 two-input NANDs).
d. To see why this works, consider the following table showing
current state, J and K inputs, resulting input to the RS flip-flop,
and resulting new state:
Q J K R S Q
before after
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 0 1 1
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
(Again, we require that the RS be edge-triggered to prevent
instability.)
e. The JK flip-flop is the most general type of flip-flop.
For this reason, JK's are the most broadly useful type (though
D's have the advantage of one fewer input).
f. DEMONSTRATE (File JK flip flop)
3. Clocked flip-flops are often built with additional asynchronous
set and/or clear inputs which can set or clear the state independent
of the clock. (These are used, for example, to clear the flip-flop
when the system it is part of is first powered-up.)
a. The following shows a how a master-slave JK flip-flop can be built
with this capability:
Preset
------------------+-----------------------------+
| |
J _____ | _____ _____ | _____
--------| \ +--| \ | \ +--| \ Q
(to Q')--------| A )o----| C )o-+------| E )o----| G )o--+-------
+--|_____/ +--|_____/ | +--|_____/ +--|_____/ |
| | | | | |
| +------------)-+ | +-------------)--+
| |\ | | | | |
-----+--| >o------------------)-)-+ | |
Clock | |/ | | | | |
| _____________| | | ______________| |
| _____ | _____ | | _____ | _____ |
+--| \ +--| \ | +--| \ +--| \ |
(to Q) --------| B )o----| D )o---+----| F )o----| H )o-----+----
--------|_____/ +--|_____/ |_____/ +--|_____/ Q'
K | |
| |
------------------+-----------------------------+
Clear
DEMONSTRATE (File JK Flip Flop with clear - note demo only has CLR)
b. In this particular circuit, the Preset and Clear inputs are ACTIVE
LOW. (Their normal state is high.) Observe how a low on one of
these lines effectively sets or clears both the master and the
slave flip-flop, independent of the clock.
c. The following symbol can be used for a flip-flop like the above:
|
o
-------
| PR | (Note the use of the bubbles on the
| | asynchronous preset and clear inputs to
---|J Q |--- signify that they are active low)
| |
--o|> |
| |\
---|K Q'|---
| |
| CLR |
-------
o
|
d. Note carefully some terminology:
i. The effect of the J and K inputs is SYNCHRONOUS - it only
takes effect when the next clock pulse appears.
ii. The effect of the Clear and preset inputs is ASYNCHRONOUS -
their effect is felt immediately.
F. We have described flip-flop behavior by using a transition table
which gives the new state as a function of the present state and inputs.
This is what we need if we know the state and inputs and wosj to
determine the new state. Sometimes, though, we know the state we are
in and the state we wish to be in, and need to know the inputs required.
For this purpose, we can consult an EXCITATION TABLE. For example, the
following is an excitation table for a JK flip-flop:
Current State Desired State Needed Inputs
J K
0 0 0 -
0 1 1 -
1 0 - 1
1 1 - 0
Here, the hyphens indicate don't cares: the value of the specified
input is immaterial in terms of getting the flip-flop to the
desired state. Taking advantage of these can simplify associated
combinatorial logic.
III. Implementing Registers using Flip-Flops
--- ------------ --------- ----- ----------
A. One of the most common uses of flip-flops is to implement registers.
1. In the case of a CPU, these may be visible to the programmer - e.g.
the registers accessed by the various Z80 instructions you used in
lab.
2. They may be invisible to the programmer - e.g. buffer registers used
in transferring data to or from the memory system.
B. The simplest sort of register would simply consist of some number of
flip flops, perhaps with their clocks and asynchronous clear and/or
preset inputs tied together.
1. For example, the following is a 4 bit register of this sort (here
implemented with D flip-flops having asynchronous clears but not
presets.):
A A A A
3 2 1 0
| | | |
_____ | _____ | _____ | _____ |
+-|D |-+ +-|D |-+ +-|D |-+ +-|D |-+
| | | | | | | | | | | |
+-)-|> | +-)-|> | +-)-|> | +-)-|> |
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | |
| | ----- | | ----- | | ----- | | -----
| | o | | o | | o | | o
Clear | | | | | | | | | | | |
---------)-)---+---------)-)---+---------)-)---+---------)-)---+
| | | | | | | |
---------+-)-------------+-)-------------+-)-------------+ |
Clock | | | |
| | | |
I I I I
3 2 1 0
2. At any given time, the contents of the register is available on
outputs A3 .. A0.
3. The register may be cleared to all zeroes but asserting the clear
line (to low in this case.)
4. Whenever a clock pulse appears, the register will latch the
current value appearing on the four inputs I3 .. I0, and will
hold it until the next clock pulse or clear operation.
C. Of course, a typical system will contain many registers - probably all
connected to a common clock. Generally, we do not want every register
to change state on every clock - only selected ones. The following
adds to the register shown above an additional LOAD ENABLE input, such
that the register only responds to a clock pulse by accepting a new value
when the enable input is high:
A A A A
3 2 1 0
| | | |
_____ | _____ | _____ | _____ |
+-|D |-+ +-|D |-+ +-|D |-+ +-|D |-+
| | | | | | | | | | | | | | | |
+-)-|> | | +-)-|> | | +-)-|> | | +-)-|> | |
| | | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | |
| | ----- | | | ----- | | | ----- | | | ----- |
| | | | | | | | | | | |
| | | | | | | | | | | |
---------+-)-------)-----+-)-------)-----+-)-------)-----+ | |
Clock | | | | | | | |
^ | ^ | ^ | ^ |
/ \ | / \ | / \ | / \ |
| | | | | | | | | | | |
_---_ | _---_ | _---_ | _---_ |
| | | | | | | | | | | |
- - | - - | - - | - - |
/ \ / \ | / \ / \ | / \ / \ | / \ / \ |
| | | | | | | | | | | | | | | | | | | |
Load --- --- | --- --- | --- --- | --- --- |
Enable | | | |____| | | | |____| | | | |____| | | | |____|
--+--------)-+-)-----------)-+-)-----------)-+-)-----------)-+ |
| |\ | | | | | | | |
+--| >o--)---+-----------)---+-----------)---+-----------)---+
|/ | | | |
I I I I
3 2 1 0
1. Observe that the D input of flip-flop n receives input as follows:
D = (Enable)*I + (Enable)' * A
n n n
2. This serves to ensure that the register only changes state when
Enable is high, as follows:
a. The flip-flop will change state on every clock pulse, latching
the current value of D.
b. If Enable is high, then the first term in the above will be In
and the second will be 0, so the value latched will be In.
c. However, if Enable is low, then the first term is zero and the
second is An, so what the flip-flop will latch is simply a
copy of its current value; thus, it will remain in the same
state - as desired.
3. DEMONSTRATE: (File: Register with Load Enable)
D. Another kind of register that is often useful is the SHIFT REGISTER:
1. The following is an example of a 4-bit shift register, implemented with
D flip-flops, having both a common clock and a common asynchronous
clear:
A A A A
3 2 1 0
| | | |
_____ | _____ | _____ | _____ |
+-|D |-+---------|D |-+---------|D |-+---------|D |-+
| | | | | | | | |
+-)-|> | +---|> | +---|> | +---|> |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | ----- | ----- | ----- | -----
| | o | o | o | o
Clear | | | | | | | | |
---------)-)---+---------)-----+---------)-----+---------)-----+
| | | | |
---------+-)-------------+---------------+---------------+
Clock |
|
I
2. At any given time, the contents of the register is available on
outputs A3 .. A0.
3. The register may be cleared to all zeroes but asserting the clear
line (to low in this case.)
4. Whenever a clock pulse appears, the register will behave as follows:
a. The left-most flip-flop will be loaded from the external input.
b. Each of the other three flip-flops will receive the value in
its left neighbor.
c. This kind of shift register is called a RIGHT-SHIFT register,
because each clock pulse results in the data in it moving one
bit to the right, with a new bit coming in on the left and the
rightmost bit being lost.
5. Obviously, one could build a left-shift register in similar fashion,
by just connecting the D input of each flip-flop to its right
neighbor instead.
6. One could also build a shift register with an enable input as follows
(just one typical stage shown here for simplicity.)
+------------------------------+
| ____ |
____________ +---| \ |
Shift Enable | )--+ ____ |
-------------|____/ |_\ \ ----- | To input gating
) >--|D |---+-------
Shift Enable ____ -/___/ | | of right neighbor
-------------| \ | +-|> |
| )--+ | | |
-------------|____/ | | |
To output of left neighbor | -----
| o
| |
Clock Clear
NOTE: Shift Enable/Enable', Clock and Clear are common to all stages in
the register.
E. One can also build bi-directional shift registers, even including a
parallel load capability.
1. Such a register might be capable of performing one of the following
on each clock pulse:
a. No change
b. Left shift
c. Right shift
d. Parallel load
2. One way to do this is to use a 4x1 MUX and a D flip flop for each
stage, with two common control lines connecting to all stages.
The control lines (which we will call S1 and S0) might be decoded as
follows:
00 = No change
01 = Left shift
10 = Right shift
11 = Parallel load
3. A typical stage (stage i) might look like this:
A
i
|
+------------------------------------+
| ----- |
| +---------------|D |---+--- To input gating for stages i-1, i+1
| | | |
| ---------- +--|> |
| S1 ---| 4 x 1 | | | |
| S0 ---| MUX | | | |
| ---------- | -----
| | | | | | o
+--------+ A A | | |
i-1 i+1| | |
| | |
| | |
I Clock Clear
i
NOTE: S1, S0, Clock and Clear are common to all stages
F. Complete systems generally consist of several registers, interconnected
so as to allow information to move between them as needed. Such
interconnections can be either serial or parallel.
1. Serial systems are built out of shift registers, and require
only one wire between any pair of registers to allow data to flow
from one to the other. However, for n-bit registers, n clock pulses
are needed to accomplish the transfer.
a. In earlier times, whole systems could be built this way to keep
hardware complexity down (at the price of speed). But this is
seldom expedient today.
b. However, since single-wire connections are common for connecting
computer systems to slow-speed peripherals like terminals, serial
transfer is used in subsystems such as terminal interfaces.
2. Parallel systems are built out of registers with parallel load, and
require n wires between any pair of registers to allow data to flow
from one to the other. However, only 1 clock pulse is needed to
accomplish a transfer. Most systems today are largely parallel.
IV. Counters
-- --------
A. Another interesting sort of sequential circuit is the counter - a register
whose value goes up (or down) on each clock pulse.
1. The following is an example of a 4-bit counter with asynchronous
clear whose values go 0000 0001 0010 00011 ... 1111 0000 on
successive clock pulses:
------ ------ ------ ------
1 -+---|J Q| 1 -+---|J Q| 1 -+---|J Q| 1 -+---|J Q|
| | | | | | | | | | | |
Count ---)---|> | +-----)---|> | +-----)---|> | +-----)---|> |
| | | | | | | | | | | | | | |
+---|K Q'|-+ +---|K Q'|-+ +---|K Q'|-+ +---|K Q'|
------ ------ ------ ------
(Assume that the clock is triggered on the RISING edge)
a. Observe that the least significant bit is on the left.
b. This is called a RIPPLE COUNTER because the state changes ripple
down from one stage to the next. In particular, when the counter is
going from 1111 to 0000, each stage would change state just slightly
after the previous one.
DEMONSTRATE (File Ripple Counter. Note how ripple effect can be
seen - simulation parameters have been adjusted to
make this visible)
2. It is also possible to build a similar counter whose operation is
totally synchronous - i.e. all outputs change state at once:
| | |
| ___ | ___ | ___
+-------)-| \ +-------)-| \ +-------)-| \
| _____ | | )-| _____ | | )-| _____ | | )-+ _____
+-|J |-+-|___/ |-|J |-+-|___/ |-|J |-+-|___/ |-|J |
| | | | | | | | | | | |
+-)-|> | +--)-|> | +-)-|> | +-)-|> |
| | | | | | | | | | | | | | | |
| +-|K | | +-|K | | +-|K | | +-|K |
| | ----- | ----- | ----- | -----
| | o | o | o | o
Clear | | | | | | | | |
---------)-)---+---------)------+----------)-----+----------)-----+
| | | | |
---------+-)-------------+-----------------+----------------+
Clock |
|
Count Enable
a. Observe that the J and K inputs of each flip-flop are wired
together. Thus, on each clock pulse, a given flip-flop either
stays in the same state (both 0) or toggles (both 1).
b. No flip-flop changes state if Count Enable is low. (Observe
how this propagates through the stages.)
c. The first stage - which represents the least significant bit -
toggles on every clock if Count Enable is high.
d. Each other stage toggles only if its predecessor is toggling
and is currently 1 - i.e. is going from 1 to 0.
e. DEMONSTRATE (File Synchronous Counter)
3. Other kinds of counters are possible - e.g. modulo 10 counters,
modulo 12, etc. The book give some examples of these.
V. Sequential Control Circuits.
- ---------- ------- --------
A. We have seen that digital circuits are of two basic types:
1. Combinatorial circuits have outputs that at any given time are a
function only of the current inputs. Such circuits are used in
many places - for example, in the ALU to do operations like addition,
logical or, and; comparison.
2. Sequential circuits have outputs that are a function of both current
input and the history of the circuit - ie. what pattern of inputs have
been applied in the past. Such circuits are not only useful as
memories but also in the control portion of the CPU and other K's.
In particular, we will see that there is a straightforward way to
design a FINITE STATE MACHINE having any desired behavior.
3. A typical sequential circuit has an external clock for synchronization,
one or more inputs, one or more flip-flops, and one or more outputs.
Combinatorial networks are used as part of the sequential circuit for
a. Determining the next state to be assumed upon the arrival of a
clock pulse.
b. Deriving the outputs.
B. Sequential circuits are most easily designed or analyzed by working with
a STATE DIAGRAM. Each state represents one possible value of the
different flip-flops - i.e. a sequential circuit with n flip flops
can have up to 2^n states. Edges between states, labelled with possible
inputs, show the various transitions between states.
C. As an example of designing a sequential control circuit this way,
consider a controller for a traffic light to be positioned at an
intersection between a north-south and an east-west street. For
simplicity, we assume only red and green lights plus a walk light, so
that the following patterns may be displayed:
N-S street E-W street
R G
G R
Walk Walk
1. Ordinarily, the light changes from one Green-Red state to the other
every 30 seconds.
2. However, if a pedestrian is pushing a walk button at the time of a
change, then he gets a 30 second walk cycle. (This is unrealistic;
normally the system would remember any push of the button within the
cycle. We could add this simply later.)
3. We can view the controller as a black box:
_____________________
Walk _______________| |__________ N-S lights
Button | |
| |---------- E-W lights
Clock ______________| |
(one pulse every |_____________________|---------- Walk lights
30 seconds)
This black box has (not counting the clock) one input and 3 outputs.
We will designated the input as w (where 1 means the button is
being pushed), and the outputs as follows:
NS = state of North-South signals 0 = Red, 1 = Green
EW = state of East-West signals 0 = Red, 1 = Green
WL = state of Walk lights 0 = off, 1 = on
4. Its behavior can be described by a state machine with 4 states and a
state diagram as follows (where w = 0 means walk not pushed; w = 1
means walk pushed):
--> ( B / --
/ NS = 0 \ w = 0, 1
w = 1 / EW = 0 \
/ WL = 1 ) v
( A / w = 0 ( C /
NS = 1 -----------------> NS = 0
EW = 0 <----------------- EW = 1
WL = 0 ) w = 0 WL = 0 )
\ ^
w = 1 \ / w = 0, 1
\ /
--> ( D / --
NS = 0
EW = 0
WL = 1 )
a. In state A, traffic is moving north-south
b. In state C, traffic is moving east-west
c. States B and D are walk states. We need two separate states
for this to "remember" which way traffic is to flow after the
walk state completes.
d. When in states A or C, the next state depends on the input.
When in states B and D, the next state is independent of the input.
(We do not allow two successive walk cycles.)
5. To build this device, we would need a minimum of two flip flops, since
2^2 gives 4 states. One immediate question is how to associate
flip flop values with states. We will (arbitrarily) choose the
following pattern. (In practice, one may consider several different
assignments and choose the one giving the simplest overall
circuit.)
State Flip flop values
A 00
B 01
C 10
D 11
6. Outputs are now derived as follows:
State NS EW WL
00 1 0 0
01 0 0 1
10 0 1 0
11 0 0 1
If we label the two flips flop outputs Q1 and Q0, then the derivation of
the outputs from the states is as follows
NS = Q1' * Q0'
EW = Q1 * Q0'
WL = Q0
7. We also need to derive the control inputs to the flip flops (J1, K1
and J0, K0). We want to implement the following transition table:
[PUT UP ALL OF THE BELOW EXCEPT RIGHT HAND COLUMNS]
Present Input Next FF Inputs
State State
Q1 Q0 w Q1 Q0 J1 K1 J0 K0
0 0 0 1 0 1 - 0 -
0 0 1 0 1 0 - 1 -
0 1 0 1 0 1 - - 1
0 1 1 1 0 1 - - 1
1 0 0 0 0 - 1 0 -
1 0 1 1 1 - 0 1 -
1 1 0 0 0 - 1 - 1
1 1 1 0 0 - 1 - 1
8. We can now determine the values of J1, K1, J0, and K0 by using
the excitation tables for JK flip flops [PUT UP RIGHT COLUMNS]
9. We can now derive the following equations for the flip-flop
inputs by inspection or by using Karnaugh maps:
____ ____
J1 = Q0 + w' = Q0'w K1 = Q0 + w' = Q0'w
J0 = w K0 = 1
10. Finally, we can now build the circuit as follows (only control
part shown - not outputs):
+----------------------------+
| ____ |
w ------------+-| \ ------ | ------
| >o-+--|J Q1| +----------------|J Q0|
+-------|____/ | | | | |
| | | | | |
| | | |\ | |\
| +--|K |-- Vcc ---|K |------+
| ------ ------ |
| |
| |
+---------------------------------------------------------------+
(Notice how the boolean expressions turned out to give us nice
one-level NAND realizations!)
NOTE: CLOCK CONNECTIONS TO THE TWO FLIP-FLOPS ARE NOT SHOWN. THIS
IS COMMON PRACTICE TO REDUCE DIAGRAM COMPLEXITY. WE ASSUME
CONNECTIONS TO THE FLIP-FLOP CLOCK INPUTS JUST AS WE ASSUME
CONNECTIONS TO THE POWER PINS.
11. Adding memory for walk button
It would be nice if the circuit would "remember" when the walk
button is pushed, so that a pedestrian would not have to continually
lean on the button until the light changes. Our system so far is
synchronous, changing states only on clock pulses. In this case,
though, we need an asynchronous circuit that can change state
whenever the button is pushed. A single asynchronous RS flip flop
(with active low inputs) will suffice.
a. We ultimately want to connect the walk button to the set input.
b. We observe that Q0 = 1 implies that a walk request has been
granted, so we connect Q0' to the reset input (recall it is
active low).
c. To prevent an inconsistent input from arising, we allow the
reset input to INHIBIT the set input, as follows:
____
Walk button ------| \ ______
(H means it | >o-----o| |----- w input to rest of circuit
is pushed) +--|____/ | |
| | |
+---------------o| |
| ------
|
To Q0'
D. In the above example, the outputs were a function only of the state,
not of the input. (The input served only to control state transitions.)
Thus, the outputs were recorded in the state nodes of the diagram.
Such a system is called a MOORE CIRCUIT.
It is also possible to have a sequential circuit where the output is
a function BOTH of the state and of the input. In this case, we
record the output on the edges of the state diagram, separated from
the inputs by a slash. This is called a MEALY CIRCUIT.
Example: A divide-by-three counter which outputs one 1 for every 3
1's seen as input (not necessarily in succession.) After outputting
a 1, it starts counting all over again.
1. To build this, will need three states, corresponding to 0, 1, or
2 1's seen so far.
2. We have the following state diagram (here we number the states
to match the count of 1's seen):
0/0 0/0 0/0
____ ____ ____
/ \ / \ / \
\ / 1/0 \ / 1/0 \ /
( 0 ) ---------> ( 1 ) ----------> ( 2 ) -
/ \
\_____________________<______________________/
1/1
3. State table:
Current Input Next Output Excitation
State State
Q1 Q0 Enable (E) Q1 Q0 Carry(C) J1 K1 J0 K0
0 0 0 0 0 0 0 - 0 -
0 0 1 0 1 0 0 - 1 -
0 1 0 0 1 0 0 - - 0
0 1 1 1 0 0 1 - - 1
1 0 0 1 0 0 - 0 0 -
1 0 1 0 0 1 - 1 0 -
1 1 0 - - - - - - -
1 1 1 - - - - - - -
J1 = (Q0)E K1 = E J0 = (Q1')E K0 = E
output: C = (Q1)E
4. Circuit: (Have class draw)
Copyright ©2001 - Russell C. Bjork